1. Field of the Invention
This invention relates to the field of semiconductor memories.
2. Prior Art
Recently there has been more interest in fabricating three-dimensional (3D) memory arrays, that is, memories having cells disposed at numerous levels above a substrate. Each level includes a plurality of spaced-apart first lines extending in one direction. The first lines are vertically separated from a plurality of parallel spaced-apart second lines running in a second direction, for example, extending perpendicular to the first lines. Memory cells are disposed between the first lines and second lines at the projected intersection of the lines. These memories are described in U.S. Pat. Nos. 5,835,396 and 6,034,882.
In U.S. patent application Ser. No. 09/560,626 filed Apr. 28, 2000, entitled “Three-Dimensional Memory Array and Method of Fabrication,” a 3D memory is described using rail-stacks which define both the lines and the memory cells of an array. Each cell includes an antifuse layer. A diode is formed once the cell is programmed. In a subsequent application, Ser. No. 09/814,727 filed Mar. 21, 2001, entitled “Three-Dimensional Memory Array and Method of Fabrication,” an improved 3D memory also employing rail-stacks is described. In this application, P+N− diodes are used to reduce leakage current.
The present invention is an improvement of the memory described in the above-referenced applications. It permits better scalability and lower leakage current, as will be described.